With the progress in the art of miniaturization process and the resulting increase in the storage capacity of the semiconductor storage device, the test time of the semiconductor storage device by a tester or the like, is increasing to raise costs in the test and hence in those in products. For shortening the test time of the semiconductor storage device, use of parallel test is taken to be effective. The schematics of the typical conventional parallel test are hereinafter described. In case of a semiconductor storage device, having e.g. a four-bank structure, the device is tested by activation on the bank basis, in the normal operation (normal testing). In the parallel test, when a given bank is activated, the totality of the banks in the semiconductor storage device are activated simultaneously. The write test (WRITE) and read test (READ) are carried out in this state to achieve the shortening of the test time.
In case the semiconductor storage device is tested using a tester, the maximum test frequency of which is low, testing the device by activation on the bank basis leads to prolonged test time because of the low test frequency. For this reason, the parallel test is used.
For testing the semiconductor memory, having plural banks, reference may be made to the description of the Patent document 1, cited below. In this Patent document 1, the testing and the interleaving bank control for a semiconductor storage device, which includes a command decoder, a control signal latch circuit for each bank, a mode register, a test mode decoder and a test mode decision circuit, and also includes a memory cell array, an X decoder, a Y decoder and a sense amplifier, is disclosed. In the Patent document 2, cited below, there is disclosed a memory device in which, when the writing operation is carried out in parallel on plural flash memories, the timing of applying the write voltage is offset from one flash memory to another to reduce the peak of the write current produced in parallel writing in the plural flash memories and hence the write time by write interleaving.
FIG. 3 is a diagram showing the configuration of a conventional semiconductor storage device during parallel test. Specifically, FIG. 3 schematically depicts, in a block diagram, a typical circuit configuration of a conventional semiconductor storage device, which has a plural number of banks, a command decoder circuit, and a circuit for generating control signals associated with the respective banks, as disclosed in the Patent document 1, recited below. FIG. 4 depicts a waveform diagram for illustrating the operation of the conventional semiconductor storage device during the parallel test.
In FIG. 3, a command decoder 301 receives a clock signal CLK and a plural number of command signals (a set of external command signals) supplied from outside the semiconductor storage device, and decodes the command signals to generate internal control signals.
Among command signals, entered to a command decoder 301, in e.g. a clock synchronization type SDRAM (synchronous DRAM) or a DDR (double data rate SDRAM), there are, for examples, bank-active (ACT), read (READ), write (WRITE), pre-charge (PRE; pre-charging of a selected bank), mode register setting (MRS) and auto-refresh (REF). The write operation is executed on receipt of a write command in the ROW active state. That is, a ROW address bank active command (ACT) is entered to activate a bank in interest (activate a specified ROW address), a write command (WRITE) and a column address (COLUMN) are supplied after a certain time as from the input of the bank active command, and data is written in an address specified in accordance with the burst length as set in a mode register, not shown. A pre-charge command then is entered and subsequently the bank is in an idle state. The read operation is executed on receipt of the read command in the row active state. That is, the ROW address and the bank active command (ACT) are entered to activate the bank (that is, activate the particular ROW address). After a preset time as from the input of the bank active command, the read command (READ) and the column address are entered, and read data of the address specified in accordance with a preset burst length and the CAS latency is output. Subsequently, a pre-charge command (PRE) is entered and the bank in interest is then in an idle state.
The circuit block 302A and 302B are control blocks which receive respectively bank activating signals ACTA and ACTB, output from the command decoder 301 and generate respectively strobe signals RASBA and RASBB for activating internal ROW systems of the two banks. The circuit block 302B is a control block for the bank B, corresponding to the circuit block 302A for the bank A.
Circuit blocks 303A and 305A are control blocks which receive the RASBA signal for activating the bank A and generate control signals needed in the ROW system. Among needed control signals, there are e.g. a signal controlling an X-address (one-shot pulse signal controlling the activation period of the selected word line) and a signal controlling an X redundancy circuit, not shown. The circuit block 305A controls the time for securing a restore level in a memory cell, not shown (the amount of electric charge held in a cell). The signal output from the circuit block 305A is RTOA.
With the circuit block 303A being an X-address control block, the circuit block 304A is a circuit block receiving the X-address to select a word line of the associated bank.
Circuit blocks 303B and 305B are control blocks which receive the RASBA signal for activating the bank B and generate control signals needed in the ROW system. Among needed control signals, there are e.g. a signal controlling an X-address (one-shot pulse signal controlling the activation period of the selected word line) and a signal controlling the X redundancy circuit, not shown. The circuit block 305B controls the time for securing a restore level (the amount of electric charge held in a cell) in a memory cell, not shown. The signal output from the circuit block 305A is RTOA.
The circuit block 303B is an X-address control block and the circuit block 304B is a circuit block receiving the X-address to select a word line.
If an external signal is supplied to the semiconductor storage device for activating the bank A during the normal operation (normal operation other than the test operation and normal testing other than the parallel test), the command decoder 301 generates the A bank activating signal ACTA, while the circuit block 302A receives the A bank activating signal ACTA to generate the strobe signal RASBA for driving the ROW system circuit for the bank A. The strobe signal RASBA becomes an input to a variety of ROW system control blocks.
If an external signal is supplied for activating the bank B, the command decoder 301 generates the B bank activating signal ACTB, while there is generated the strobe signal RASBB for driving the ROW system circuit for the associated bank.
If, in the configuration shown in FIG. 3, a bank active command (ACT) for an arbitrary bank is entered during parallel test from outside, the command decoder 301 simultaneously generates bank activation signals ACTA and ACTB, in synchronization with the rising edge of the external clock signal CLK, for activating the totality of the banks, here the bank A and the bank B. The strobe signals RASBA and RASBB (which are active at a low level) for driving the ROW system circuits for the banks A and B, are generated, based on the bank activation signals ACTA and ACTB, such that the activation of the bank A and that of the bank B start simultaneously. The test time may be made shorter by this structure.
[Patent Document 1]
    Japanese Patent Kokai Publication No.JP-A-11-45599 (pages 5 and 6, FIG. 2)[Patent Document 2]    Japanese Patent Kokai Publication No.JP-A-11-242632 (pages 3 to 6, FIGS. 1 and 3)[Non-Patent Document 1]    ‘Method for Using SDRAM’, chapter 7, Basic Operation Mode, pages 56 to 60, Internet (retrieved on Aug. 4, 2003), Elpida Memory <URL>http.//WWW.elpida.com/pdfs/JO123N50.pdf